As an example of semiconductor devices to which this invention relates, there is a semiconductor device described in Japanese Patent Application No. 2005-349857 (Patent Document 1) proposed by the present inventors. Patent Document 1 proposes the semiconductor device provided with a circuit having at least one pair of transistors of different conductivity types in which at least one of the transistors includes at least a semiconductor layer formed on an SOI base substrate, a gate insulating layer covering at least a part of a surface thereof, and a gate electrode formed on the gate insulating film, and is formed as a normally-off accumulation mode transistor. A material of the gate electrode and an impurity concentration of the semiconductor layer are selected in such a manner that a thickness of a depletion layer formed in the semiconductor layer by a difference in work function (work function difference) between the gate electrode and the semiconductor layer is greater than a film thickness of the semiconductor layer.
Further, Patent Document 1 discloses that, for the purpose of equalizing current driving capabilities of a p-channel transistor and an n-channel transistor constituting CMOS transistors, the current driving capability of the p-channel transistor can be enhanced by using a (110) plane of silicon. According to this structure, switching speeds of the n-channel transistor and the p-channel transistor can substantially be equalized and areas occupied by electrodes formed on channel regions can substantially be equalized.
Patent Document 1: Japanese Patent Application No. 2005-349857